This book constitutes the proceedings of the 15th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2013, held in Santa Barbara, CA, USA, in August 2013. The 27 papers presented were carefully reviewed and selected from 132 submissions. The papers are organized in the following topical sections: side-channel attacks; physical unclonable function; lightweight cryptography; hardware implementations and fault attacks; efficient and secure implementations; elliptic curve cryptography; masking; side-channel attacks and countermeasures.

Handbook of Signal Processing Systems is organized in three parts. The first part motivates representative applications that drive and apply state-of-the art methods for design and implementation of signal processing systems; the second part discusses architectures for implementing these applications; the third part focuses on compilers and simulation tools, describes models of computation and their associated design tools and methodologies. This handbook is an essential tool for professionals in many fields and researchers of all levels.

This book presents the methodologies and for embedded systems design, using field programmable gate array (FPGA) devices, for the most modern applications. Coverage includes state-of-the-art research from academia and industry on a wide range of topics, including applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration.

This book uses motivating examples and real-life attack scenarios to introduce readers to the general concept of fault attacks in cryptography. It offers insights into how the fault tolerance theories developed in the book can actually be implemented, with a particular focus on a wide spectrum of fault models and practical fault injection techniques, ranging from simple, low-cost techniques to high-end equipment-based methods. It then individually examines fault attack vulnerabilities in symmetric, asymmetric and authenticated encryption systems. This is followed by extensive coverage of countermeasure techniques and fault tolerant architectures that attempt to thwart such vulnerabilities. Lastly, it presents a case study of a comprehensive FPGA-based fault tolerant architecture for AES-128, which brings together of a number of the fault tolerance techniques presented. It concludes with a discussion on how fault tolerance can be combined with side channel security to achieve protection against implementation-based attacks. The text is supported by illustrative diagrams, algorithms, tables and diagrams presenting real-world experimental results.

Circuits and Systems for Security and Privacy begins by introducing the basic theoretical concepts and arithmetic used in algorithms for security and cryptography, and by reviewing the fundamental building blocks of cryptographic systems. It then analyzes the advantages and disadvantages of real-world implementations that not only optimize power, area, and throughput but also resist side-channel attacks. Merging the perspectives of experts from industry and academia, the book provides valuable insight and necessary background for the design of security-aware circuits and systems as well as efficient accelerators used in security applications.

Based on the historical development of so-called Crypto Chips, the current Transformation of Cryptography shows numerous changes, innovations and new process designs in the field of Cryptography, which also need to be integrated in a hardware design of Microprocessors and Microcontrollers for a Secure Embedded System. Using the example of the encrypting Echo protocol, a design of a hardware architecture based on three Chips is presented: The central Echo Chip #1 represents a "Trusted Execution Environment" (TEE), which is not connected to the Internet for the conversion processes from plain text to cipher text and is supposed to remain quasi original, to prevent software injections or possible uploads of copies of the plain text. The technical specifications of all three microprocessors are described in detail. The established paradigm of separation is recognized as a security feature and discussed as a perception for a Next Generation of Microcontrollers in the field of Mobile Messaging under the technical term "Going the Extra Mile". This security architecture is then discussed in the context of seven different current risk cases with the consolidated result that the well-known OSI (Open Systems Interconnection) Model is expanded to the Secure Architecture Model, abbreviated SAM.

IT policies are set in place to streamline the preparation and development of information communication technologies in a particular setting. IT Policy and Ethics: Concepts, Methodologies, Tools, and Applications is a comprehensive collection of research on the features of modern organizations in order to advance the understanding of IT standards. This is an essential reference source for researchers, scholars, policymakers, and IT managers as well as organizations interested in carrying out research in IT policies.

This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade. Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems. This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of, and trust in, modern society’s microelectronic-supported infrastructures.

This book provides a comprehensive introduction to hardware security, from specification to implementation. Applications discussed include embedded systems ranging from small RFID tags to satellites orbiting the earth. The authors describe a design and synthesis flow, which will transform a given circuit into a secure design incorporating counter-measures against fault attacks. In order to address the conflict between testability and security, the authors describe innovative design-for-testability (DFT) computer-aided design (CAD) tools that support security challenges, engineered for compliance with existing, commercial tools. Secure protocols are discussed, which protect access to necessary test infrastructures and enable the design of secure access controllers.