This book provides a detailed overview of detection algorithms for multiple-input multiple-output (MIMO) communications systems focusing on their hardware realisation. The book begins by analysing the maximum likelihood detector, which provides the optimal bit error rate performance in an uncoded communications system. However, the maximum likelihood detector experiences a high complexity that scales exponentially with the number of antennas, which makes it impractical for real-time communications systems. The authors proceed to discuss lower-complexity detection algorithms such as zero-forcing, sphere decoding, and the K-best algorithm, with the aid of detailed algorithmic analysis and several MATLAB code examples. Furthermore, different design examples of MIMO detection algorithms and their hardware implementation results are presented and discussed. Finally, an ASIC design flow for implementing MIMO detection algorithms in hardware is provided, including the system simulation and modelling steps and register transfer level modelling using hardware description languages. Provides an overview of MIMO detection algorithms and discusses their corresponding hardware implementations in detail; Highlights architectural considerations of MIMO detectors in achieving low power consumption and high throughput; Discusses design tradeoffs that will guide readers’ efforts when implementing MIMO algorithms in hardware; Describes a broad range of implementations of different MIMO detectors, enabling readers to make informed design decisions based on their application requirements.

This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.

Now available in a three-volume set, this updated and expanded edition of the bestselling The Digital Signal Processing Handbook continues to provide the engineering community with authoritative coverage of the fundamental and specialized aspects of information-bearing signals in digital form. Encompassing essential background material, technical details, standards, and software, the second edition reflects cutting-edge information on signal processing algorithms and protocols related to speech, audio, multimedia, and video processing technology associated with standards ranging from WiMax to MP3 audio, low-power/high-performance DSPs, color image processing, and chips on video. Drawing on the experience of leading engineers, researchers, and scholars, the three-volume set contains 29 new chapters that address multimedia and Internet technologies, tomography, radar systems, architecture, standards, and future applications in speech, acoustics, video, radar, and telecommunications. This volume, Wireless, Networking, Radar, Sensor Array Processing, and Nonlinear Signal Processing, provides complete coverage of the foundations of signal processing related to wireless, radar, space–time coding, and mobile communications, together with associated applications to networking, storage, and communications.

This book contains extended and revised versions of the best papers presented at the 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, held in Madrid, Spain, in September 2010. The 14 papers included in the book were carefully reviewed and selected from the 52 full papers presented at the conference. The papers cover a wide variety of excellence in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of theses systems.

This volume of Smart Innovation, Systems and Technologies contains accepted papers presented in IIH-MSP-2016, the 12th International Conference on Intelligent Information Hiding and Multimedia Signal Processing. The conference this year was technically co-sponsored by Tainan Chapter of IEEE Signal Processing Society, Fujian University of Technology, Chaoyang University of Technology, Taiwan Association for Web Intelligence Consortium, Fujian Provincial Key Laboratory of Big Data Mining and Applications (Fujian University of Technology), and Harbin Institute of Technology Shenzhen Graduate School. IIH-MSP 2016 is held in 21-23, November, 2016 in Kaohsiung, Taiwan. The conference is an international forum for the researchers and professionals in all areas of information hiding and multimedia signal processing.

The Second Edition of OFDM Baseband Receiver Design for Wirless Communications, this book expands on the earlier edition with enhanced coverage of MIMO techniques, additional baseband algorithms, and more IC design examples. The authors cover the full range of OFDM technology, from theories and algorithms to architectures and circuits. The book gives a concise yet comprehensive look at digital communication fundamentals before explaining signal processing algorithms in receivers. The authors give detailed treatment of hardware issues - from architecture to IC implementation. Links OFDM and MIMO theory with hardware implementation Enables the reader to transfer communication received concepts into hardware; design wireless receivers with acceptable implemntation loss; achieve low-power designs Covers the latest standards, such as DVB-T2, WiMax, LTE and LTE-A Includes more baseband algorithms, like soft-decoding algorithms such as BCJR and SOVA Expanded treatment of channel models, detection algorithms and MIMO techniques Features concrete design examples of WiMAX systems and cognitive radio apllications Companion website with lecture slides for instructors Based on materials developed for a course in digital communication IC design, this book is ideal for graduate students and researchers in VLSI design, wireless communications, and communications signal processing. Practicing engineers working on algorithms or hardware for wireless communications devices will also find this to be a key reference.

This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G.

This is a comprehensive reference for readers wanting to learn about the entire range of relevant aspects in wireless communications.

This volume contains 95 papers presented at FICTA 2014: Third International Conference on Frontiers in Intelligent Computing: Theory and Applications. The conference was held during 14-15, November, 2014 at Bhubaneswar, Odisha, India. This volume contains papers mainly focused on Data Warehousing and Mining, Machine Learning, Mobile and Ubiquitous Computing, AI, E-commerce & Distributed Computing and Soft Computing, Evolutionary Computing, Bio-inspired Computing and its Applications.