This book guides readers through the design of hardware architectures using VHDL for digital communication and image processing applications that require performance computing. Further it includes the description of all the VHDL-related notions, such as language, levels of abstraction, combinational vs. sequential logic, structural and behavioral description, digital circuit design, and finite state machines. It also includes numerous examples to make the concepts presented in text more easily understandable.

Beginning in the mid 1980's, VLSI technology had begun to advance in two directions. Pushing the limit of integration, ULSI (Ultra Large Scale Integration) represents the frontier of the semiconductor processing technology in the campaign to conquer the submicron realm. The application of ULSI, however, is at present largely confined in the area of memory designs, and as such, its impact on traditional, microprocessor-based system design is modest. If advancement in this direction is merely a natural extrapolation from the previous integration generations, then the rise of ASIC (Application-Specific Integrated Circuit) is an unequivocal signal that a directional change in the discipline of system design is in effect. In contrast to ULSI, ASIC employs only well proven technology, and hence is usually at least one generation behind the most advanced processing technology. In spite of this apparent disadvantage, ASIC has become the mainstream of VLSI design and the technology base of numerous entrepreneurial opportunities ranging from PC clones to supercomputers. Unlike ULSI whose complexity can be hidden inside a memory chip or a standard component and thus can be accommodated by traditional system design methods, ASIC requires system designers to master a much larger body of knowledge spanning from processing technology and circuit techniques to architecture principles and algorithm characteristics. Integrating knowledge in these various areas has become the precondition for integrating devices and functions into an ASIC chip in a market-oriented environment. But knowledge is of two kinds.

Rapid Prototyping of Application Specific Signal Processors presents leading-edge research that focuses on design methodology, infrastructure support and scalable architectures developed by the 150 million dollar DARPA United States Department of Defense RASSP Program. The contributions to this edited work include an introductory overview chapter that explains the origin, concepts and status of this effort. The RASSP Program is a multi-year DARPA/Tri-Service initiative intended to dramatically improve the process by which complex digital systems, particularly embedded signal processors, are designed, manufactured, upgraded and supported. This program was originally driven by military applications for signal processing. The requirements of military applications for real-time signal processing are typically more demanding than those of commercial applications, but the time gap between technology employed in advanced military prototypes and commercial products is narrowing rapidly. The research on methodologies, infrastructure and architectures presented in this book is applicable to commercial signal processing systems that are in design now, or will be developed before the end of the decade. Rapid Prototyping of Application Specific Signal Processors is a valuable reference for developers of embedded digital systems, particularly systems engineers for signal processing systems (such as digital TV, biomedical image processing systems and telecommunications) and for military contractors who are developing signal processing systems. This book will also be of interest to managers who are charged with responsibility for creating and maintaining environments and infrastructures for developing large embedded digital systems. The chief value for managers will be the defining of methods and processes that reduce development time and cost.

Introduction to Hardware-Software Co-Design presents a number of issues of fundamental importance for the design of integrated hardware software products such as embedded, communication, and multimedia systems. This book is a comprehensive introduction to the fundamentals of hardware/software co-design. Co-design is still a new field but one which has substantially matured over the past few years. This book, written by leading international experts, covers all the major topics including: fundamental issues in co-design; hardware/software co-synthesis algorithms; prototyping and emulation; target architectures; compiler techniques; specification and verification; system-level specification. Special chapters describe in detail several leading-edge co-design systems including Cosyma, LYCOS, and Cosmos. Introduction to Hardware-Software Co-Design contains sufficient material for use by teachers and students in an advanced course of hardware/software co-design. It also contains extensive explanation of the fundamental concepts of the subject and the necessary background to bring practitioners up-to-date on this increasingly important topic.

ThesearetheproceedingsofCHES2002,theFourthWorkshoponCryptographic Hardware and Embedded Systems. After the ?rst two CHES Workshops held in Massachusetts, and the third held in Europe, this is the ?rst Workshop on the West Coast of the United States. There was a record number of submissions this year and in response the technical program was extended to 3 days. As is evident by the papers in these proceedings, there have been again many excellent submissions. Selecting the papers for this year’s CHES was not an easy task, and we regret that we could not accept many contributions due to the limited availability of time. There were 101 submissions this year, of which 39 were selected for presentation. We continue to observe a steady increase over previous years: 42 submissions at CHES ’99, 51 at CHES 2000, and 66 at CHES 2001. We interpret this as a continuing need for a workshop series that c- bines theory and practice for integrating strong security features into modern communicationsandcomputerapplications. Inadditiontothesubmittedcont- butions, Jean-Jacques Quisquater (UCL, Belgium), Sanjay Sarma (MIT, USA) and a panel of experts on hardware random number generation gave invited talks. As in the previous years, the focus of the Workshop is on all aspects of cr- tographic hardware and embedded system security. Of special interest were c- tributionsthatdescribenewmethodsfore?cienthardwareimplementationsand high-speed software for embedded systems, e. g. , smart cards, microprocessors, DSPs, etc. CHES also continues to be an important forum for new theoretical and practical ?ndings in the important and growing ?eld of side-channel attacks.

Current multimedia and telecom applications require complex, heterogeneous multiprocessor system on chip (MPSoC) architectures with specific communication infrastructure in order to achieve the required performance. Heterogeneous MPSoC includes different types of processing units (DSP, microcontroller, ASIP) and different communication schemes (fast links, non standard memory organization and access). Programming an MPSoC requires the generation of efficient software running on MPSoC from a high level environment, by using the characteristics of the architecture. This task is known to be tedious and error prone, because it requires a combination of high level programming environments with low level software design. This book gives an overview of concepts related to embedded software design for MPSoC. It details a full software design approach, allowing systematic, high-level mapping of software applications on heterogeneous MPSoC. This approach is based on gradual refinement of hardware/software interfaces and simulation models allowing to validate the software at different abstraction levels. This book combines Simulink for high level programming and SystemC for the low level software development. This approach is illustrated with multiple examples of application software and MPSoC architectures that can be used for deep understanding of software design for MPSoC.

Fuzzy hardware developments have been a major force driving the applications of fuzzy set theory and fuzzy logic in both science and engineering. This volume provides the reader with a comprehensive up-to-date look at recent works describing new innovative developments of fuzzy hardware. An important research trend is the design of improved fuzzy hardware. There is an increasing interest in both analog and digital implementations of fuzzy controllers in particular and fuzzy systems in general. Specialized analog and digital VLSI implementations of fuzzy systems, in the form of dedicated architectures, aim at the highest implementation efficiency. This particular efficiency is asserted in terms of processing speed and silicon utilization. Processing speed in particular has caught the attention of developers of fuzzy hardware and researchers in the field. The volume includes detailed material on a variety of fuzzy hardware related topics such as: Historical review of fuzzy hardware research Fuzzy hardware based on encoded trapezoids Pulse stream techniques for fuzzy hardware Hardware realization of fuzzy neural networks Design of analog neuro-fuzzy systems in CMOS digital technologies Fuzzy controller synthesis method Automatic design of digital and analog neuro-fuzzy controllers Electronic implementation of complex controllers Silicon compilation of fuzzy hardware systems Digital fuzzy hardware processing Parallel processor architecture for real-time fuzzy applications Fuzzy cellular systems Fuzzy Hardware: Architectures and Applications is a technical reference book for researchers, engineers and scientists interested in fuzzy systems in general and in building fuzzy systems in particular.

This title serves as an introduction ans reference for the field, with the papers that have shaped the hardware/software co-design since its inception in the early 90s.

The book is divided into four major parts. Part I covers HDL constructs and synthesis of basic digital circuits. Part II provides an overview of embedded software development with the emphasis on low-level I/O access and drivers. Part III demonstrates the design and development of hardware and software for several complex I/O peripherals, including PS2 keyboard and mouse, a graphic video controller, an audio codec, and an SD (secure digital) card. Part IV provides three case studies of the integration of hardware accelerators, including a custom GCD (greatest common divisor) circuit, a Mandelbrot set fractal circuit, and an audio synthesizer based on DDFS (direct digital frequency synthesis) methodology. The book utilizes FPGA devices, Nios II soft-core processor, and development platform from Altera Co., which is one of the two main FPGA manufactures. Altera has a generous university program that provides free software and discounted prototyping boards for educational institutions (details at http://www.altera.com/university). The two main educational prototyping boards are known as DE1 ($99) and DE2 ($269). All experiments can be implemented and tested with these boards. A board combined with this book becomes a “turn-key” solution for the SoPC design experiments and projects. Most HDL and C codes in the book are device independent and can be adapted by other prototyping boards as long as a board has similar I/O configuration.

Today more than 90% of all programmable processors are employed in embedded systems. The LISA processor design platform presented in this book addresses recent design challenges and results in highly satisfactory solutions, covering all major high-level phases of embedded processor design.