The papers included in this issue of ECS Transactions were originally presented in the symposium ¿Low k Inter-Level Metal Dielectrics and New Contact and Barrier Metallurgies/Structures¿, held during the PRiME 2008 joint international meeting of The Electrochemical Society and The Electrochemical Society of Japan, with the technical cosponsorship of the Japan Society of Applied Physics, the Korean Electrochemical Society, the Electrochemistry Division of the Royal Australian Chemical Institute, and the Chinese Society of Electrochemistry. This meeting was held in Honolulu, Hawaii, from October 12 to 17, 2008.

In Advanced ULSI interconnects – fundamentals and applications we bring a comprehensive description of copper-based interconnect technology for ultra-lar- scale integration (ULSI) technology for integrated circuit (IC) application. In- grated circuit technology is the base for all modern electronics systems. You can ?nd electronics systems today everywhere: from toys and home appliances to a- planes and space shuttles. Electronics systems form the hardware that together with software are the bases of the modern information society. The rapid growth and vast exploitation of modern electronics system create a strong demand for new and improved electronic circuits as demonstrated by the amazing progress in the ?eld of ULSI technology. This progress is well described by the famous “Moore’s law” which states, in its most general form, that all the metrics that describe integrated circuit performance (e. g. , speed, number of devices, chip area) improve expon- tially as a function of time. For example, the number of components per chip d- bles every 18 months and the critical dimension on a chip has shrunk by 50% every 2 years on average in the last 30 years. This rapid growth in integrated circuits te- nology results in highly complex integrated circuits with an increasing number of interconnects on chips and between the chip and its package. The complexity of the interconnect network on chips involves an increasing number of metal lines per interconnect level, more interconnect levels, and at the same time a reduction in the interconnect line critical dimensions.