Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI Architectures for Modern Error-Correcting Codes serves as a bridge connecting advancements in coding theory to practical hardware implementations. Instead of focusing on circuit-level design techniques, the book highlights integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation. The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can be also used as a reference for graduate-level courses on VLSI design and error-correcting coding. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included. More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures.

The four volume set assembled following The 2005 International Conference on Computational Science and its Applications, ICCSA 2005, held in Suntec International Convention and Exhibition Centre, Singapore, from 9 May 2005 till 12 May 2005, represents the ?ne collection of 540 refereed papers selected from nearly 2,700 submissions. Computational Science has ?rmly established itself as a vital part of many scienti?c investigations, a?ecting researchers and practitioners in areas ranging from applications such as aerospace and automotive, to emerging technologies such as bioinformatics and nanotechnologies, to core disciplines such as ma- ematics, physics, and chemistry. Due to the shear size of many challenges in computational science, the use of supercomputing, parallel processing, and - phisticated algorithms is inevitable and becomes a part of fundamental t- oretical research as well as endeavors in emerging ?elds. Together, these far reaching scienti?c areas contribute to shape this Conference in the realms of state-of-the-art computational science research and applications, encompassing the facilitating theoretical foundations and the innovative applications of such results in other areas.

Information theory is an exceptional field in many ways. Technically, it is one of the rare fields in which mathematical results and insights have led directly to significant engineering payoffs. Professionally, it is a field that has sustained a remarkable degree of community, collegiality and high standards. James L. Massey, whose work in the field is honored here, embodies the highest standards of the profession in his own career. The book covers the latest work on: block coding, convolutional coding, cryptography, and information theory. The 44 contributions represent a cross-section of the world's leading scholars, scientists and researchers in information theory and communication. The book is rounded off with an index and a bibliography of publications by James Massey.

This book constitutes the refereed proceedings of the 8th Annual International Computing and Combinatorics Conference, COCOON 2002, held in Singapore in August 2002. The 60 revised full papers presented together with three invited contributions were carefully reviewed and selected from 106 submissions. The papers are organized in topical sections on complexity theory, discrete algorithms, computational biology and learning theory, radio networks, automata and formal languages, Internet networks, computational geometry, combinatorial optimization, and quantum computing.

The papers comprising Vol. I and Vol. II were prepared for and presented at the International Conference on Information Networking 2002 (ICOIN 2002), which was held from January 30 to February 1, 2002 at Cheju Island, Korea. It was organized by the KISS (Korean Information Science Society) SIGIN in Korea, IPSJ SIG DPE (Distributed Processing Systems) in Japan, the ITRI (Industrial Technology Research Institute), and National Taiwan University in Taiwan. The papers were selected through two steps, refereeing and presentation review. We selected for the theme of the conference the motto “One World of Information Networking”. We did this because we believe that networking will transform the world into one zone, in spite of different ages, countries and societies. Networking is in the main stream of everyday life and affects directly millions of people around the world. We are in an era of tremendous excitement for professionals working in many aspects of the converging networking, information retailing, entertainment, and publishing companies. Ubiquitous communication and computing technologies are changing the world. Online communities, e commerce, e service, and distance learning are a few of the consequences of these technologies, and advanced networking will develop new applications and technologies with global impact. The goal is the creation of a world wide distributed computing system that connects people and appliances through wireless and high bandwidth wired channels with a backbone of computers that serve as databases and object servers. Thus, Vol.

As distinct from other security and cryptography conferences, the Information Security Conference (ISC) 2002 brought together individuals involved in a wide variety of different disciplines of information security to foster the exchange of ideas. The conference is an outgrowth of the Information Security Workshop, first held in Ishikawa, Japan 1997. ISC 2002 was held in Sao Paulo, Brazil, on September 30– October 2, 2002. The Program Committee considered 81 submissions of which 38 papers were accepted for presentation. These proceedings contain revised versions of the accepted papers. The papers provide a representative sample of both the variety and the truly international scope of information security research conducted currently. The topics addressed range from e-commerce protocols to access control and trust management, and to cryptography and cryptographic algorithms. Many people deserve our gratitude for their contribution to the success of the conference. We would like to thank the General Chair, Routo Terada, for overseeing the local arrangements, including registration and maintaining the conference website, and for the smooth running of the conference. We are grateful to Robbie Ye for his expert help in processing the electronic submissions, reviews and acceptance notifications. Robbie’s enthusiasm and energy greatly simplified the Program Committee’s task of conducting the on-line evaluation of the submitted papers under tight time constraints.

"This book focuses on wireless sensor networks and their operation, covering topics including routing, energy efficiency and management"--

This book constitutes the refereed proceedings of the 16th International Symposium on VSLI Design and Test, VDAT 2012, held in Shibpur, India, in July 2012. The 30 revised regular papers presented together with 10 short papers and 13 poster sessions were carefully selected from 135 submissions. The papers are organized in topical sections on VLSI design, design and modeling of digital circuits and systems, testing and verification, design for testability, testing memories and regular logic arrays, embedded systems: hardware/software co-design and verification, emerging technology: nanoscale computing and nanotechnology.