Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI Architectures for Modern Error-Correcting Codes serves as a bridge connecting advancements in coding theory to practical hardware implementations. Instead of focusing on circuit-level design techniques, the book highlights integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation. The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can be also used as a reference for graduate-level courses on VLSI design and error-correcting coding. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included. More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures.

The process of Integrated Circuits (IC) started its era of VLSI (Very Large Scale Integration) in 1970’s when thousands of transistors were integrated into one single chip. Nowadays we are able to integrate more than a billion transistors on a single chip. However, the term “VLSI” is still being used, though there was some effort to coin a new term ULSI (Ultra-Large Scale Integration) for fine distinctions many years ago. VLSI technology has brought tremendous benefits to our everyday life since its occurrence. VLSI circuits are used everywhere, real applications include microprocessors in a personal computer or workstation, chips in a graphic card, digital camera or camcorder, chips in a cell phone or a portable computing device, and embedded processors in an automobile, et al. VLSI covers many phases of design and fabrication of integrated circuits. For a commercial chip design, it involves system definition, VLSI architecture design and optimization, RTL (register transfer language) coding, (pre- and post-synthesis) simulation and verification, synthesis, place and route, timing analyses and timing closure, and multi-step semiconductor device fabrication including wafer processing, die preparation, IC packaging and testing, et al. As the process technology scales down, hundreds or even thousands of millions of transistors are integrated into one single chip. Hence, more and more complicated systems can be integrated into a single chip, the so-called System-on-chip (SoC), which brings to VLSI engineers ever increasingly challenges to master techniques in various phases of VLSI design. For modern SoC design, practical applications are usually speed hungry. For instance, Ethernet standard has evolved from 10Mbps to 10Gbps. Now the specification for 100Mbps Ethernet is on the way. On the other hand, with the popularity of wireless and portable computing devices, low power consumption has become extremely critical. To meet these contradicting requirements, VLSI designers have to perform optimizations at all levels of design. This book is intended to cover a wide range of VLSI design topics. The book can be roughly partitioned into four parts. Part I is mainly focused on algorithmic level and architectural level VLSI design and optimization for image and video signal processing systems. Part II addresses VLSI design optimizations for cryptography and error correction coding. Part III discusses general SoC design techniques as well as other application-specific VLSI design optimizations. The last part will cover generic nano-scale circuit-level design techniques.

For the new millenium, Wai-Kai Chen introduced a monumental reference for the design, analysis, and prediction of VLSI circuits: The VLSI Handbook. Still a valuable tool for dealing with the most dynamic field in engineering, this second edition includes 13 sections comprising nearly 100 chapters focused on the key concepts, models, and equations. Written by a stellar international panel of expert contributors, this handbook is a reliable, comprehensive resource for real answers to practical problems. It emphasizes fundamental theory underlying professional applications and also reflects key areas of industrial and research focus. WHAT'S IN THE SECOND EDITION? Sections on... Low-power electronics and design VLSI signal processing Chapters on... CMOS fabrication Content-addressable memory Compound semiconductor RF circuits High-speed circuit design principles SiGe HBT technology Bipolar junction transistor amplifiers Performance modeling and analysis using SystemC Design languages, expanded from two chapters to twelve Testing of digital systems Structured for convenient navigation and loaded with practical solutions, The VLSI Handbook, Second Edition remains the first choice for answers to the problems and challenges faced daily in engineering practice.

This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.

This book addresses challenges faced by both the algorithm designer and the chip designer, who need to deal with the ongoing increase of algorithmic complexity and required data throughput for today’s mobile applications. The focus is on implementation aspects and implementation constraints of individual components that are needed in transceivers for current standards, such as UMTS, LTE, WiMAX and DVB-S2. The application domain is the so called outer receiver, which comprises the channel coding, interleaving stages, modulator, and multiple antenna transmission. Throughout the book, the focus is on advanced algorithms that are actually in use in modern communications systems. Their basic principles are always derived with a focus on the resulting communications and implementation performance. As a result, this book serves as a valuable reference for two, typically disparate audiences in communication systems and hardware design.

This book provides a detailed overview of detection algorithms for multiple-input multiple-output (MIMO) communications systems focusing on their hardware realisation. The book begins by analysing the maximum likelihood detector, which provides the optimal bit error rate performance in an uncoded communications system. However, the maximum likelihood detector experiences a high complexity that scales exponentially with the number of antennas, which makes it impractical for real-time communications systems. The authors proceed to discuss lower-complexity detection algorithms such as zero-forcing, sphere decoding, and the K-best algorithm, with the aid of detailed algorithmic analysis and several MATLAB code examples. Furthermore, different design examples of MIMO detection algorithms and their hardware implementation results are presented and discussed. Finally, an ASIC design flow for implementing MIMO detection algorithms in hardware is provided, including the system simulation and modelling steps and register transfer level modelling using hardware description languages. Provides an overview of MIMO detection algorithms and discusses their corresponding hardware implementations in detail; Highlights architectural considerations of MIMO detectors in achieving low power consumption and high throughput; Discusses design tradeoffs that will guide readers’ efforts when implementing MIMO algorithms in hardware; Describes a broad range of implementations of different MIMO detectors, enabling readers to make informed design decisions based on their application requirements.

Covering the fast evolving area of advanced coding, Error Control Coding for B3G/4G Wireless Systems targets IMT-Advanced systems to present the latest findings and implementation solutions. The book begins by detailing the fundamentals of advanced coding techniques such as Coding, Decoding, Design, and Optimization. It provides not only state-of-the-art research findings in 3D Turbo-codes, non-binary LDPC Codes, Fountain, and Raptor codes, but also insights into their real-world implementation by examining hardware architecture solutions, for example VLSI complexity, FPGA, and ASIC. Furthermore, special attention is paid to Incremental redundancy techniques, which constitute a key feature of Wireless Systems. A promising application of these advanced coding techniques, the Turbo-principle (also known as iterative processing), is illustrated through an in-depth discussion of Turbo-MIMO, Turbo-Equalization, and Turbo-Interleaving techniques. Finally, the book presents the status of major standardization activities currently implementing such techniques, with special interest in 3GPP UMTS, LTE, WiMAX, IEEE 802.11n, DVB-RCS, DVB-S2, and IEEE 802.22. As a result, the book coherently brings together academic and industry vision by providing readers with a uniquely comprehensive view of the whole topic, whilst also giving an understanding of leading-edge techniques. Includes detailed coverage of coding, decoding, design, and optimization approaches for advanced codes Provides up to date research findings from both highly reputed academics and industry standpoints Presents the latest status of standardization activities for Wireless Systems related to advanced coding Describes real-world implementation aspects by giving insights into architecture solutions for both LDPC and Turbo-codes Examines the most advanced and promising concepts of turbo-processing applications: Turbo-MIMO, Turbo-Equalization, Turbo-Interleaving

This book discusses new, efficient and hardware realizable algorithms that can attain the performance of beyond 5G wireless communication. The authors explain topics gradually, stepping from basic MIMO detection to optimized schemes for both hard and soft domain MIMO detection and also to the feasible VLSI implementation, scalable to any MIMO configuration (including massive MIMO, used in satellite/space communication). The techniques described in this book enable readers to implement real designs, with reduced computational complexity and improved performance.