Modern complementary metal oxide semiconductor (CMOS) digital-to-analog converters (DACs) are limited in their bandwidth due to technological constraints. These limitations can be overcome by parallel DAC architectures, which are called interleaving concepts. Christian Schmidt analyzes the limitations and the potential of two innovative DAC interleaving concepts to provide the basis for a practical implementation: the analog multiplexing DAC (AMUX-DAC) and the frequency interleaving DAC (FI-DAC). He presents analytical and discrete-time models as a theoretical foundation and develops digital signal processing (DSP) algorithms to compensate the analog impairments. Further, he quantifies the impact of various limiting parameters with numerical simulations and verifies both concepts in laboratory experiments. About the Author: Christian Schmidt works at the Fraunhofer Heinrich-Hertz-Institute, Berlin, Germany, on innovative solutions for broadband signal generation in the field of optical communications. The studies for his dissertation were carried out at the Technische Universität Berlin and at the Fraunhofer Heinrich-Hertz-Institute, both Berlin, Germany.

This book gathers selected high-quality research papers presented at the Eighth International Congress on Information and Communication Technology, held at Brunel University, London, on 20–23 February 2023. It discusses emerging topics pertaining to information and communication technology (ICT) for managerial applications, e-governance, e-agriculture, e-education and computing technologies, the Internet of Things (IoT) and e-mining. Written by respected experts and researchers working on ICT, the book offers a valuable asset for young researchers involved in advanced studies. The work is presented in four volumes.

Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for highdata-ate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconguration for multiple radio standards. ?? DACs can t very well into this trend of digital architectures as they contain a large digital signal processing component and oer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction lter order is reduced. Achieving a large bandwidth from ?? DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ?? DAC architectures, even in nanometer CMOS processes. Time-interleaved ?? (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs. The rst work is an 8-GS/s interleaved ?? DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ?? modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the nal multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, –57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to be limited by the testing setup for sending high-speed digital data into the prototype. The performance of a two-channel interleaved ?? DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this eect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 — z—1)n. It is shown that a low-order FIR lter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this lter is also developed. These expressions are useful for choosing a suitable modulator and lter order for an interleaved ?? DAC in the early stage of the design process. A comparison between the FIR lter and compensation techniques for DCE mitigation is also presented. The nal work is a 11 GS/s 1.1 GHz bandwidth time-interleaved DAC prototype IC in 65-nm CMOS for the 60-GHz radio baseband. The high sampling rate is again achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output i.e only fteen analog current cells. The single clock architecture for the logic and the multiplexing requires each channel to operate at 5.5 GHz. To enable this, a new look-ahead technique is proposed that decouples the two channels within the modulator feedback path thereby improving the speed as compared to conventional loop-unrolling. Full speed DAC testing is enabled by an on-chip 1 Kb memory whose read path also operates at 5.5 GHz. Measurement results from the prototype show that the ?? DAC achieves >53 dB SFDR, < —49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. The proposed ?? DAC can satisfy the spectral mask of the 60-GHz radio IEEE 802.11ad WiGig standard with a second order reconstruction lter.

Advances in Analog and RF IC Design for Wireless Communication Systems gives technical introductions to the latest and most significant topics in the area of circuit design of analog/RF ICs for wireless communication systems, emphasizing wireless infrastructure rather than handsets. The book ranges from very high performance circuits for complex wireless infrastructure systems to selected highly integrated systems for handsets and mobile devices. Coverage includes power amplifiers, low-noise amplifiers, modulators, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), and even single-chip radios. This book offers a quick grasp of emerging research topics in RF integrated circuit design and their potential applications, with brief introductions to key topics followed by references to specialist papers for further reading. All of the chapters, compiled by editors well known in their field, have been authored by renowned experts in the subject. Each includes a complete introduction, followed by the relevant most significant and recent results on the topic at hand. This book gives researchers in industry and universities a quick grasp of the most important developments in analog and RF integrated circuit design. - Emerging research topics in RF IC design and its potential application - Case studies and practical implementation examples - Covers fundamental building blocks of a cellular base station system and satellite infrastructure - Insights from the experts on the design and the technology trade-offs, the challenges and open questions they often face - References to specialist papers for further reading

Analog Circuit Design contains the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 18 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of: Smart Data Converters: Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology, Filters on Chip: Chaired by Herman Casier, AMI Semiconductor Fellow, Multimode Transmitters: Chaired by Prof. M. Steyaert, Catholic University Leuven, Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design.

This comprehensive new handbook is a one-stop engineering reference covering data converter fundamentals, techniques, and applications. Beginning with the basic theoretical elements necessary for a complete understanding of data converters, the book covers all the latest advances made in this changing field. Details are provided on the design of high-speec ADCs, high accuracy DACs and ADCs, sample-and-hold amplifiers, voltage sources and current reference,noise-shaping coding, sigma-delta converters, and much more.

This paper reviews recent developments of interleaved Successive Approximation Analog-to-Digital converters (SAR) in deep sub-micron CMOS technologies. The discussion covers design tradeoffs and degrees of freedom related to the impact of extensive interleaving with many SAR units on bandwidth, noise, linearity, and spurious performance. The impact of interleaving mismatches on representative broadband and multi-carrier narrowband signals is also discussed. Next, two examples are given demonstrating how interleaving with many ADCs can be transformed from a weakness to a strength. The first example concerns low spurious performance enabled by redundant SAR converters and randomization of their operation. The second example presents spectral sensing techniques.

This textbook is appropriate for use in graduate-level curricula in analog-to-digital conversion, as well as for practicing engineers in need of a state-of-the-art reference on data converters. It discusses various analog-to-digital conversion principles, including sampling, quantization, reference generation, Nyquist architectures and sigma-delta modulation. This book presents an overview of the state-of-the-art in this field and focuses on issues of optimizing accuracy and speed, while reducing the power level. This new, fourth edition emphasizes novel calibration concepts, the specific requirements of systems, the consequences of advanced technology and the need for a more statistical approach to accuracy. Pedagogical enhancements to this edition include additional, new exercises, solved examples to introduce all key, new concepts and warnings, remarks and hints, from a practitioner's perspective, wherever appropriate. Considerable background information and practical tips, from designing a PCB, to lay-out aspects, to trade-offs on system level, complement the discussion of basic principles, making this book a valuable reference for the experienced engineer.

This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

The book focuses on design technology of high-speed and high-performance direct digital frequency synthesizer (DDS) chip. The technologies involves phase to amplitude converter design, D/A converter design, phase accumulator design, multi-chip synchronization circuit design, etc. In each chapter, the concept of the technology is explained first, and then the features of different implementation schemes are introduced through the real design cases. More over, a design case of a 2.5GHz monolithic DDS in 0.18 μm CMOS which was designed by the authors are introduced in detail, which can help the reader understanding about the of DDS design deeply. The book is suitable for the readers who are interested to learn practical design technology in DDS. The book can benefit researchers, engineers, and graduate students in fields of mix-signal IC design, communication engineering, electronics engineering, and radar engineering, etc.