This detailed book addresses three main areas of solid state electronics, providing an insight into the state of the art in material and device research that will be of interest to all those involved in compound semiconductors.

Primary goal of this book is to provide a cohesive description of the vast field of semiconductor quantum devices, with special emphasis on basic quantum-mechanical phenomena governing the electro-optical response of new-generation nanomaterials. The book will cover within a common language different types of optoelectronic nanodevices, including quantum-cascade laser sources and detectors, few-electron/exciton quantum devices, and semiconductor-based quantum logic gates. The distinguishing feature of the present volume is a unified microscopic treatment of quantum-transport and coherent-optics phenomena on ultrasmall space- and time-scales, as well as of their semiclassical counterparts.

The operation of semiconductor devices depends upon the use of electrical potential barriers (such as gate depletion) in controlling the carrier densities (electrons and holes) and their transport. Although a successful device design is quite complicated and involves many aspects, the device engineering is mostly to devise a "best" device design by defIning optimal device structures and manipulating impurity profIles to obtain optimal control of the carrier flow through the device. This becomes increasingly diffIcult as the device scale becomes smaller and smaller. Since the introduction of integrated circuits, the number of individual transistors on a single chip has doubled approximately every three years. As the number of devices has grown, the critical dimension of the smallest feature, such as a gate length (which is related to the transport length defIning the channel), has consequently declined. The reduction of this design rule proceeds approximately by a factor of 1. 4 each generation, which means we will be using 0. 1-0. 15 ). lm rules for the 4 Gb chips a decade from now. If we continue this extrapolation, current technology will require 30 nm design rules, and a cell 3 2 size