This book provides a comprehensive overview of the state-of-the-art, data flow-based techniques for the analysis, modeling and mapping technologies of concurrent applications on multi-processors. The authors present a flow for designing embedded hard/firm real-time multiprocessor streaming applications, based on data flow formalisms, with a particular focus on wireless modem applications. Architectures are described for the design tools and run-time scheduling and resource management of such a platform.

This book introduces a generic and systematic design-time/run-time methodology for handling the dynamic nature of modern embedded systems, without adding large safety margins in the design. The techniques introduced can be utilized on top of most existing static mapping methodologies to deal effectively with dynamism and to increase drastically their efficiency. This methodology is based on the concept of system scenarios, which group system behaviors that are similar from a multi-dimensional cost perspective, such as resource requirements, delay, and energy consumption. Readers will be enabled to design systems capable to adapt to current inputs, improving system quality and/or reducing cost, possibly learning on-the-fly during execution. Provides an effective solution to deal with dynamic system design Includes a broad survey of the state-of-the-art approaches in this domain Enables readers to design for substantial cost improvements (e.g. energy reductions), by exploiting system scenarios Demonstrates how the methodology has been applied effectively on various, real design problems in the embedded system context

In this new edition of the Handbook of Signal Processing Systems, many of the chapters from the previous editions have been updated, and several new chapters have been added. The new contributions include chapters on signal processing methods for light field displays, throughput analysis of dataflow graphs, modeling for reconfigurable signal processing systems, fast Fourier transform architectures, deep neural networks, programmable architectures for histogram of oriented gradients processing, high dynamic range video coding, system-on-chip architectures for data analytics, analysis of finite word-length effects in fixed-point systems, and models of architecture. There are more than 700 tables and illustrations; in this edition over 300 are in color. This new edition of the handbook is organized in three parts. Part I motivates representative applications that drive and apply state-of-the art methods for design and implementation of signal processing systems; Part II discusses architectures for implementing these applications; and Part III focuses on compilers, as well as models of computation and their associated design tools and methodologies.

This edited volume presents the latest high-quality technical contributions and research results in the areas of computing, informatics, and information management. The book deals with state-of art topics, discussing challenges and possible solutions, and explores future research directions. The main goal of this volume is not only to summarize new research findings but also place these in the context of past work. This volume is designed for professional audience, composed of researchers, practitioners, scientists and engineers in both the academia and the industry.

VLSI 2010 Annual Symposium will present extended versions of the best papers presented in ISVLSI 2010 conference. The areas covered by the papers will include among others: Emerging Trends in VLSI, Nanoelectronics, Molecular, Biological and Quantum Computing. MEMS, VLSI Circuits and Systems, Field-programmable and Reconfigurable Systems, System Level Design, System-on-a-Chip Design, Application-Specific Low Power, VLSI System Design, System Issues in Complexity, Low Power, Heat Dissipation, Power Awareness in VLSI Design, Test and Verification, Mixed-Signal Design and Analysis, Electrical/Packaging Co-Design, Physical Design, Intellectual property creating and sharing.

This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors’ combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.

This book constitutes the thoroughly refereed proceedings of the 11th International Joint Conference on Software Technologies, ICSOFT 2016, held in Lisbon, Portugal, in July 2016. The 13 revised full papers together with 3 short papers presented were carefully reviewed and selected from 84 submissions. The papers selected to be included in this book contribute to the understanding of relevant trends of current research on software technologies, including: Modelling for mobile devices Software and system testing Model-driven software development Reengineering systems for multi-tenancy Embedded and real-time systems reconguration Domain-specic languages and modelling Software and systems quality Context-aware and dynamically adapting software systems

This book constitutes the refereed proceedings of the 8th IFIP International Conference on Network and Parallel Computing, NPC 2011, held in Changsha, China, in October 2011. The 28 papers presented were carefully reviewed selected from 54 submissions. The papers are organized in the following topical sections: filesystems and data, network and parallel algorithms, cluster and grid, trust and authentication, and monitor, diagnose, and then optimize.

Verification of real-time requirements in systems-on-chip becomes more complex as more applications are integrated. Predictable and composable systems can manage the increasing complexity using formal verification and simulation. This book explains the concepts of predictability and composability and shows how to apply them to the design and analysis of a memory controller, which is a key component in any real-time system.

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.