This book aims to highlight the research activities in the domain of thermal-aware testing. Thermal-aware testing can be employed both at circuit level and at system level Describes range of algorithms for addressing thermal-aware test issue, presents comparison of temperature reduction with power-aware techniques and include results on benchmark circuits and systems for different techniques This book will be suitable for researchers working on power- and thermal-aware design and the testing of digital VLSI chips

This book describes methods to address wearout/aging degradations in electronic chips and systems, caused by several physical mechanisms at the device level. The authors introduce a novel technique called accelerated active self-healing, which fixes wearout issues by enabling accelerated recovery. Coverage includes recovery theory, experimental results, implementations and applications, across multiple nodes ranging from planar, FD-SOI to FinFET, based on both foundry provided models and predictive models. Presents novel techniques, tested with experiments on real hardware; Discusses circuit and system level wearout recovery implementations, many of these designs are portable and friendly to the standard design flow; Provides circuit-architecture-system infrastructures that enable the accelerated self-healing for future resilient systems; Discusses wearout issues at both transistor and interconnect level, providing solutions that apply to both; Includes coverage of resilient aspects of emerging applications such as IoT.

This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications. Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems; Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems; Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.

Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deep-submicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis. Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors. Advanced SoCs manufactured as 3D stacked ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be artificially accelerated using gradient-based, burn-in like, operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. A schedule-based technique that enforces the temperature-gradients for burn-in like operations is proposed in this thesis. This technique is further developed to support testing for delay-related defects while appropriate gradients are enforced. The last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safety-critical applications to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced. All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC’02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the costs, in particular the costs related to addressing thermal issues and early-life failures. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the schedule generation time by more than half.

Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.

Formal methods have been applied successfully to the verification of medium-sized programs in protocol and hardware design for some time. However, their application to the development of large systems requires more emphasis on specification, modeling, and validation techniques supporting the concepts of reusability and modifiability, and their implementation in new extensions of existing programming languages like Java. This book contains 20 revised papers submitted after the 10th Symposium on Formal Methods for Components and Objects, FMCO 2011, which was held in Turin, Italy, in October 2011. Topics covered include autonomic service-component ensembles; trustworthy eternal systems via evolving software, data, and knowledge; parallel patterns for adaptive heterogeneous multicore systems; programming for future 3D architectures with many cores; formal verification of object oriented software; and an infrastructure for reliable computer systems.

This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. It includes an overview of available EDA tool solutions and their applicability to design problems.

Physical Design for 3D Integrated Circuits reveals how to effectively and optimally design 3D integrated circuits (ICs). It also analyzes the design tools for 3D circuits while exploiting the benefits of 3D technology. The book begins by offering an overview of physical design challenges with respect to conventional 2D circuits, and then each chapter delivers an in-depth look at a specific physical design topic. This comprehensive reference: Contains extensive coverage of the physical design of 2.5D/3D ICs and monolithic 3D ICs Supplies state-of-the-art solutions for challenges unique to 3D circuit design Features contributions from renowned experts in their respective fields Physical Design for 3D Integrated Circuits provides a single, convenient source of cutting-edge information for those pursuing 2.5D/3D technology.

"This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"--

This book focuses on industrial development, design, implementation, and transformation using technologies such as Artificial Intelligence, Machine Learning, the Internet of Things (IoT), Big Data Analysis, and Blockchain. It incorporates complex processes, functions, and various other elements as one central component of digital systems. Industrial Transformation: Implementation and Essential Components and Processes of Digital Systems discusses the industry transformation aligned with the computerization of manufacturing and the required skills needed to build a new workforce. This book covers the role that AI plays in the management of resource flow and decision-making in the transformation of operations, as well as supply chain management. It presents sustainability and efficiency with IoT, Machine Learning, Data Analysis, and Blockchain technologies as it focuses on industrial development, design, and implementation. This book showcases the incorporation of complex processes and functions as one central component of digital systems and explores current trends that are working to accelerate industrial transformation. Case studies are also included, depicting the technologies that are influencing the transition into the fourth Industrial Revolution, such as industrial infrastructure, biodiversity, and enhanced productivity. This book is aimed at researchers, scholars, and students that require real-time knowledge and applications where the transformation and implementation of digital systems in the manufacturing sector are needed.