DSPs sind programmierbare, in Echtzeit arbeitende Mikroprozessoren. Dieser Band fasst erstmals das breitgefächerte, schnell expandierende Gebiet DSP-basierter Anwendungen in der Mobilkommunikation zusammen und behandelt zahlreiche Applikationen, u.a. Modems in Mobilfunknetzen, Benutzerschnittstellen (Sprache und Video), Sicherheit und Benutzererkennung. Der Leser erhält einen Eindruck von den Herausforderungen, denen sich zukünftige DSP-Anwendungen stellen müssen.

The power consumption of integrated circuits is one of the most problematic considerations affecting the design of high-performance chips and portable devices. The study of power-saving design methodologies now must also include subjects such as systems on chips, embedded software, and the future of microelectronics. Low-Power Electronics Design covers all major aspects of low-power design of ICs in deep submicron technologies and addresses emerging topics related to future design. This volume explores, in individual chapters written by expert authors, the many low-power techniques born during the past decade. It also discusses the many different domains and disciplines that impact power consumption, including processors, complex circuits, software, CAD tools, and energy sources and management. The authors delve into what many specialists predict about the future by presenting techniques that are promising but are not yet reality. They investigate nanotechnologies, optical circuits, ad hoc networks, e-textiles, as well as human powered sources of energy. Low-Power Electronics Design delivers a complete picture of today's methods for reducing power, and also illustrates the advances in chip design that may be commonplace 10 or 15 years from now.

The power consumption of microprocessors is one of the most important challenges of high-performance chips and portable devices. In chapters drawn from Piguet's recently published Low-Power Electronics Design, this volume addresses the design of low-power microprocessors in deep submicron technologies. It provides a focused reference for specialists involved in systems-on-chips, from low-power microprocessors to DSP cores, reconfigurable processors, memories, ad-hoc networks, and embedded software. Low-Power Processors and Systems on Chips is organized into three broad sections for convenient access. The first section examines the design of digital signal processors for embedded applications and techniques for reducing dynamic and static power at the electrical and system levels. The second part describes several aspects of low-power systems on chips, including hardware and embedded software aspects, efficient data storage, networks-on-chips, and applications such as routing strategies in wireless RF sensing and actuating devices. The final section discusses embedded software issues, including details on compilers, retargetable compilers, and coverification tools. Providing detailed examinations contributed by leading experts, Low-Power Processors and Systems on Chips supplies authoritative information on how to maintain high performance while lowering power consumption in modern processors and SoCs. It is a must-read for anyone designing modern computers or embedded systems.

Digital image sequences (including digital video) are increasingly common and important components in technical applications ranging from medical imaging and multimedia communications to autonomous vehicle navigation. The immense popularity of DVD video and the introduction of digital television make digital video ubiquitous in the consumer domain. Digital Image Sequence Processing, Compression, and Analysis provides an overview of the current state of the field, as analyzed by leading researchers. An invaluable resource for planning and conducting research in this area, the book conveys a unified view of potential directions for further industrial development. It offers an in-depth treatment of the latest perspectives on processing, compression, and analysis of digital image sequences. Research involving digital image sequences remains extremely active. The advent of economical sequence acquisition, storage, and display devices, together with the availability of computing power, opens new areas of opportunity. This volume delivers the background necessary to understand the strengths and weaknesses of current techniques and the directions that consumer and technical applications may take over the coming decade.

The impending advent of GSM in the early 1990s triggered massive investment that revolutionised the capability of DSP technology. A decade later, the vastly increased processing requirements and potential market of 3G has triggered a similar revolution, with a host of start-up companies claiming revolutionary technologies hoping to challenge and displace incumbent suppliers. This book, with contributions from today's major players and leading start-ups, comprehensively describes both the new approaches and the responses of the incumbents, with detailed descriptions of the design philosophy, architecture, technology maturity and software support. Analysis of SDR baseband processing requirements of cellular handsets and basestations 3G handset baseband - ASIC, DSP, parallel processing, ACM and customised programmable architectures 3G basestation baseband - DSP (including co-processors), FPGA-based approaches, reconfigurable and parallel architectures Architecture optimisation to match 3G air interface and application algorithms Evolution of existing DSP, ASIC & FPGA solutions Assessment of the architectural approaches and the implications of the trends. An essential resource for the 3G product designer, who needs to understand immediate design options within a wider context of future product roadmaps, the book will also benefit researchers and commercial managers who need to understand this rapid evolution of baseband signal processing and its industry impact.

This book is the proceedings volume of the 10th International Conference on Field Programmable Logic and its Applications (FPL), held August 27 30, 2000 in Villach, Austria, which covered areas like reconfigurable logic (RL), reconfigurable computing (RC), and its applications, and all other aspects. Its subtitle "The Roadmap to Reconfigurable Computing" reminds us, that we are currently witnessing the runaway of a breakthrough. The annual FPL series is the eldest international conference in the world covering configware and all its aspects. It was founded 1991 at Oxford University (UK) and is 2 years older than its two most important competitors usually taking place at Monterey and Napa. FPL has been held at Oxford, Vienna, Prague, Darmstadt, London, Tallinn, and Glasgow (also see: http://www. fpl. uni kl. de/FPL/). The New Case for Reconfigurable Platforms: Converging Media. Indicated by palmtops, smart mobile phones, many other portables, and consumer electronics, media such as voice, sound, video, TV, wireless, cable, telephone, and Internet continue to converge. This creates new opportunities and even necessities for reconfigurable platform usage. The new converged media require high volume, flexible, multi purpose, multi standard, low power products adaptable to support evolving standards, emerging new standards, field upgrades, bug fixes, and, to meet the needs of a growing number of different kinds of services offered to zillions of individual subscribers preferring different media mixes.

This book provides design methods for Digital Signal Processors and Application Specific Instruction set Processors, based on the author's extensive, industrial design experience. Top-down and bottom-up design methodologies are presented, providing valuable guidance for both students and practicing design engineers. Coverage includes design of internal-external data types, application specific instruction sets, micro architectures, including designs for datapath and control path, as well as memory sub systems. Integration and verification of a DSP-ASIP processor are discussed and reinforced with extensive examples. - Instruction set design for application specific processors based on fast application profiling - Micro architecture design methodology - Micro architecture design details based on real examples - Extendable architecture design protocols - Design for efficient memory sub systems (minimizing on chip memory and cost) - Real example designs based on extensive, industrial experiences

An authoritative survey of intelligent fingerprint-recognition concepts, technology, and systems is given. Editors and contributors are the leading researchers and applied R&D developers of this personal identification (biometric security) topic and technology. Biometrics and pattern recognition researchers and professionals will find the book an indispensable resource for current knowledge and technology in the field.

Adaptive techniques play a key role in modern wireless communication systems. The concept of adaptation is emphasized in the Adaptation in Wireless Communications Series through a unified framework across all layers of the wireless protocol stack ranging from the physical layer to the application layer, and from cellular systems to next-generation wireless networks. This specific volume, Adaptive Signal Processing in Wireless Communications is devoted to adaptation in the physical layer. It gives an in-depth survey of adaptive signal processing techniques used in current and future generations of wireless communication systems. Featuring the work of leading international experts, it covers adaptive channel modeling, identification and equalization, adaptive modulation and coding, adaptive multiple-input-multiple-output (MIMO) systems, and cooperative diversity. It also addresses other important aspects of adaptation in wireless communications such as hardware implementation, reconfigurable processing, and cognitive radio. A second volume in the series, Adaptation and Cross-layer Design in Wireless Networks(cat no.46039) is devoted to adaptation in the data link, network, and application layers.

Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap between the separate worlds of hardware and software design— the key feature of reconfigurable computing is its groundbreaking ability to perform computations in hardware to increase performance while retaining the flexibility of a software solution. Reconfigurable computers serve as affordable, fast, and accurate tools for developing designs ranging from single chip architectures to multi-chip and embedded systems. Scott Hauck and Andre DeHon have assembled a group of the key experts in the fields of both hardware and software computing to provide an introduction to the entire range of issues relating to reconfigurable computing. FPGAs (field programmable gate arrays) act as the "computing vehicles to implement this powerful technology. Readers will be guided into adopting a completely new way of handling existing design concerns and be able to make use of the vast opportunities possible with reconfigurable logic in this rapidly evolving field. - Designed for both hardware and software programmers - Views of reconfigurable programming beyond standard programming languages - Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways